#ifndef __ASM_CACHE_H
#define __ASM_CACHE_H

#include <asm/cachetype.h>

#define L1_CACHE_SHIFT		6
#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#ifndef __ASSEMBLY__

#ifndef ____cacheline_aligned
#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
#endif

#define __read_mostly __attribute__((__section__(".data..read_mostly")))

static inline int cache_line_size(void)
{
	u32 cwg = cache_type_cwg();

	return cwg ? 4 << cwg : L1_CACHE_BYTES;
}
void __inval_cache_range(virt_addr_t start,
					    virt_addr_t end);
#endif	/* __ASSEMBLY__ */

#endif
